Device for equalizing binary bipolar signals

ABSTRACT

The present invention is concerned with a circuit for equalizing binary bipolar signals, comprising transversal filter means for reducing distortions due to overlapping.

United States Patent 11 1 1111 3,758,863

Ungerboeck Sept. 11, 1973 1 DEVICE FOR EQUALIZING BINARY Assignee: Iiifrnafibhhlfiihs? M36151};

Corporation, Armonk, NY.

[56] References Cited UNITED STATES PATENTS 3,621,221 11/1971 Cann 333/18 3,611,149 10/1971 Kimball 325/323 Primary Examiner-Albert J. Mayer [22] Filed; o 's 971" Att0rneyR0y R. Schlemmer, Jr. et a].

The present invention is concerned with a circuit for 0] F gn Appli i Priority Data equalizing binary bipolar signals, comprising transver- Oct. 22, 1970 Switzerland 15670/70 l fil r m n f r r ing i r ions due to overlapping. [52] U.S. Cl 325/321, 325/473, 333/28 [51] Int. Cl. 1104!) 1/16 8 Clalms 9 Drawmg Figures [58] Field of Search 325/42, 65, 321-326, 325/473-476; 333/18, 28, 70 T B MATCHED ylil FILTER 1 DELAY L|NE T T T T y vyz Y Y0 Y4 Y 2 y NON LINEAR WEIGHHNG NETWORK "K(y ,.....y ,y n. y l

PATENTEDSEPI I m5 3; 758.863

SHEET 1 0F 4 11 t ATCHED m FILTER y L DELAY LiNE 1 T T =T T M 2 1 o -1 -z -M NON-LINEAR wmmmc NETWORK 'K 19 n FIG. 1

INVENTOR GOTTFRIED J. UNGERBOECK miwwm ATTORNEY PAIENIEUSEPI H 1 3, 758.863

SHEH 2 I]? 4 DEVICE FOR EQUALIZING BINARY BIPOLAR SIGNALS BACKGROUND OF THE INVENTION When binary signals, which were sent out as sequences of pulses of opposite polarity at a constant bit rate (fixed time interval T between successive pulses) are transmitted, distortions are generated by the addition of noise signals as well as by mutual overlapping of neighboring signal pulses due to linear distortions of the transmission channel. An equalizer in the receiver should be able to eliminate these distortions as much as possible.

Many types of equalizers for this purpose are known in the art; during recent years particularly, equalizers became known which include a matched filter for reduction of noise distortions followed by a transversal filter for decreasing the undesirable effects of signal overlapping. The transversal filters include a tapped delay line, the tap outputs of which are multiplied with a weighting coefficient by special circuitry and are then added to generate the output signal.

In most of the known equalizers of this type the tap output signals are linearly weighted. The weighting coefficients are either defined by solving a system of linear equations or, for an optimum linear filter, by solving a complicated system of no-linear equations by a.

method described by Aaron and Tuffs in IEEE Transactions on Information Theory, January 1966, pp. 26-34.

An optimum reduction of distortion can be achieved with linear filters only if the original signal and the received observable signal are both normally distributed. Since, however, the original binary signal has a discrete distribution of pulse amplitudes further improvement can be achieved only by non-linear filters. A non-linear equalizer is disclosed in Swiss Pat. No. 483,163. The equalizer of the Swiss patent comprises a transversal filter with non-linear amplitude limiters connected to the output taps except for the central tap. The output signal of the central tap is multiplied by two and added to the output signals of the amplitude limiters. In many cases, this equalizer offers better results than linear equalizers; it represents, however, not yet the optimum solution because of its simple construction.

SUMMARY AND OBJECTS It is an object of the present invention to disclose an equalizer which closely approximately a theoretically optimum equalizer and which provides the possibility of determining the binary signal values with minimum error probability. The sampling values of a received signal interval should be evaluated and used for correction of the central value, not individually but together as a whole. This should be achieved as follows: The sequences of binary values most probably corresponding to the received signal interval should be found and used for determining the correction term which then depends less on the tap output signals than on the binary values actually sent.

The invention in general comprises a circuit for equalizing binary bipolar signals, comprising transversal filter means for reducing distortions due to overlapping, which is characterized in that the transversal filter means include, besides means for acquiring 2M+l sampling values y from an observed current interval of the input signal, means for providing reference values 3,

corresponding to at least part of the sampling values which are generated when a single binary value is transmitted, and further includes means for non-linear evaluation and combination of sampling values and reference values in order to generate an output signal 1 ZyH-K, wherein corresponds to the difference of sig nals which are obtained in the evaluation means from sampling values and reference values and their corresponding negative values only by generating sums and by selecting maxima of these sums.

. Other objects, features and advantages of the invention will be apparent from the following description of this invention.

DESCRIPTION OF THE DRAWINGS FIG. 1 comprises a schematic representation of an equalizer circuit constructed according to the invention.

FIGS. 2A and 28 comprise waveforms illustrating a non-equalized input signal for the equalizer of FIG. 1, and an input signal partly equalized by a matched filter.

FIG. 3 comprises the waveform of a delay line filter input signal due to a single pulse representing one binary value.

FIG. 4 comprises waveforms illustrating schematically the mutual overlapping of two binary pulses.

FIG. 5A comprises a block representation of the decision element used in the equalizers of FIG. 6 and FIG. 7.

FIG. 58 comprises a schematic diagram of the circuit details of one embodiment of the decision elements of FIG. 5A.

FIG. 6 comprises a block diagram of a first embodiment of an equalizer constructed according to the invention.

FIG. 7 comprises a block diagram of a second embodiment of an equalizer constructed according to the invention.

DESCRIPTION OF THE DISCLOSED EMBODIMENTS OF THE INVENTION FIG. 1 schematically shows broadly the structure of an equalizer constructed according to the teaching of the present invention. A sequence of binary bipolar pulses with equal time distance from each other (amplitude a, i I; bit rate f HT) is applied to a transmission channel. The signal x(t) received from the transmission channel which is distorted by mutual overlapping of the binary signals and by additive noise initially passes through a matched filter 11 which constitutes the input of the equalizer. This filter is matched to the transmission characteristics of the channel and effects pre-equalizing of the received signal, particularly an optimum suppression of the noise. These processes will become more clear in connection with FIG. 2.

For further equalizing, particularly for the compensation of overlapping, the output signal of filter I1 is transferred to a delay line 13 including a number of taps the distance of which corresponding to a delay time of one bit interval T of the transmitted bipolar binary signal.

Signal y from the center tap is applied to a multiplier 15 the output signal of which is 2y All the other taps for signals y ...y y ...y are connected to evaluation unit 17 which furnishes a correction signal K at its output. Combination of signals 2y0 and K by an adder 19 renders the output signal 2(1) of the equalizer. This output signal is sampled at a bit rate corresponding to the bit rate of the binary signal; the sign of the sampling value determines the binary output value.

Evaluation unit'17 effects a nonlinear weighting of tap output signals y ,,,...y with consideration of mutual dependencies. The evaluation is termed non-linear because it comprises decision processes which select the maximum of a plurality of available terms or signals for further processing. Evaluation unit 17 and the process on which it is based comprise the essential feature of the present invention. This unit and its operation will be described later in more detail. First, however, the structure of the signals to be evaluated andthe mutual overlapping are described in somewhat more detail in connection with FIGS. 2 and 4.

In FIG. 2A the actual input signal x(r) to the equalizer is represented by the solid curve. The corresponding equation is:

A restriction to a finite sequence of binary values is made here, i.e., M values on each side of the currently considered binary value a h(t) is the response of an undisturbed transmission channel to a sent binary value a +1. The curve for c ld!) reveals that the deformed single pulse spreads over several bit intervals (n T) which factcauses the overlapping. w(t) stands for the Gaussian noise which is additively superimposed over the sum of the single pulse signals.

The solid curve in FIG. 28 represents the output signal y(t) of the matched filter l 1. This filter causes optimum noise suppression by autocorrelation. During this process, the received signals are also equalized with respect to phase, and the signals a h(tzT) il) transformed into signals a s(t1T). Due to the phase equalization, (1) is a symmetric function with respect to its maximum amplitude.

The mutual overlapping of single pulses, however, still exists at the filter output and is possibly even worse than at the filter input. The output signal of the filter which must now be processed further to eliminate the effect of overlapping can be described by equation:

In the above equation, n(t) is the remaining part of the noise. It should have no influence or a minimum of influence on the binary output value. In some prior art equalizers, however, the influence of this remaining part of the noise is even increased.

s( I) is the pulse response at the matched filter output for a single undisturbed binary pulse a =+l. This waveform is shown in FIG. 3. ss are the values of function .r(r) at successive sample times. These values could be acquired, for example, from the corresponding taps of the delay line 13 (FIG. 1) after receipt of a single undisturbed pulse. The values a; are an important input to the following part of the equalizing process, as is shown later on. They must be permanently available as auxiliary values from potentiometer taps or in a storage means after a single or repetitive measuring or calculating procedure. Over-shooting of the curve :(l) to the negative region is well possible at the extreme ends but it is not assumed here to simplify the representation.

A much simplified representation of the mutual overlapping of two binary pulses is shown in FIG. 4. The two pulses, if independent of each other, would generate the signals a s(t) and a,s(tiT) (broken curves). Due to overlapping, the solid curve in the middle is being generated. Therefore, at time t instead of a s the sampling value y is obtained which differs from a s by an amount app Consequently, the approximate value a,s has to be derived from the received and measurable value y, in order to correct the received value y so that the value a s is obtained as accurately as possible.

In most of the prior art equalizers the correction values a s (actually, there is not only one but a number of neighboring pulses a, which overlap pulse a,,) are approximately obtained by separate linear or non-linear weighting of the received values y,. The received values Yr, however, are not only dependent on the respective sending pulses a; but are also distorted by overlapping of neightboring pulses (FIG. 4 shows the influence of a on 31,). Consequently, an improved correction of overlapping can be achieved if the delay line tap output signals are not weighted individually but in combination. This is accomplished by the method utilized by the present invention which will now be described.

In the following derivation of the optimum correction term, the theoretical considerations are set forth on which the present equalizer is based. lnitially,in view of the received signal waveform within the interval of observation, two terms are established representing the probabilities that a =+I or a -I has been transmitted within an arbitrary sequence of adjacent binary signals. Starting with the ratio of these two terms, a formula for the cofrec tion term (y .u...y 1. y1...yM) is developed; an implementation of this formula would be the optimum equalizer.

The complicatgggpression for K is converted to a simpler form by approximation. To evaluate this somewhat simplified expression for K, known methods of dynamic programming are employed; this results in recursion formulae which can easily be evaluated. Finally, circuit means are disclosed for implementing and evaluating these recursion formulae.

The derivation is based on the waveform of the received signal x( t) during a considered interval I:

M I e 1 The following probability ratio can now be formulated:

l lP( i/ o )l/iP( 1 o )1 p(X,/a :1 are the probability density functions for the fact that with a =l or a =-l respectively the signal waveform X, can be received. If A 1, the output binary value b which should correspond to the sent binary value a is made +1. If A E 1, then b -l.

To convert the expression for A, the sum of the probability density functions p for all possible sequences of binary value corresponding to the interval I is now introduced. These are sequences comprising the M binary values which precede and the M binary values which follow the considered value a A sequence including the central value a IS designated a; a sequence without a is designated 3.

With these assumptions .th'filowing'in iie wEu'enE means the sum of the values p for all possible binary sequences Z. p(X,/Z) represents the probability density for receiving the signal wave. form X, when the binary sequence (Twas sent.

For calculating p(X,/Z), the signal corresponding to the sequence His substracted from the received signal. For the remaining part of the signal, which corresponds to the Gaussian noise signal, the probability density function can be derived by a known procedure. If this assumption is made, and if the values y, and s, are known for a received signal interval, equation 6 can be converted into:

It is useful to logarithmize equation 7. Insertion of the values for n cancellation of the constant terms In which M =1 ex 1 M I M I i(yi' i) EM kzM i k i-k (The apostrophes at the side of the summation symbol means that the index 0 is not considered for the summation).

When equation 8 is read in connection with FIG. 1,

it can be recognized that the two terms on the right side of the equation correspond to the input signals of summing unit 19. In FIG. 1, Ink is replaced by z(t):

Equations 7 9 correspond to the optimum non-linear equalizer. Because equation 9 is very complicated for the determination of correcting term K and because it would be difficult to implement this equation by circuit means, simplifications are now made.

The following description sets forth the derivation of a sub-optimum correction term. The logarithm of a sum of exponential functions is almost equal to the largest of the exponents, whereas the others can be neglected:

Considering this fact, equation 9 can be simplified and an approximate expression for K can be obtained which is much better suited for implementation:

The meaning of this approximate solution can be recognized by considering that the same result would have been achieved if the following had already been used instead of equation 4 Max p(X /a +1, 5

The approximate solution represented by equation 12 means that the most probable sequences 5" are determined with a +1 and a 1 respectively, and that the ratio of their probabilities is calculated.

Finally, the binary value of output signal b is made equal to +1 or -l depending upon the sign of z (t) 2y as indicated earlier on.

The manner in which the aforementioned optimization is effected will now be set forth. The determination of correction term K2 according to equation I l is an optimization problem which cannot be solved by classical methods of the calculus of variations because of the discrete character of a (a 1-1). The trivial method of inserting and evaluating all possible sequences 5 requires considerable effort for larger values of M. The

effort can be drastically reduced, however, with the aid of the dynamic programming method disclosed by R. Bellman in his book Dynamic Programming (Princeton University Press, 1957).

The problem is to find for each of the two bracketed terms in equation 1 l the optimum sequence of values a; which renders the term to a maximum (the values of y, and s being fixed). The principle set forth subsequently is used. If several values a, of the optimum sequence have already been determined it must be found out for one single additional value a, whether it must be +1 or -1 in order to achieve the optimum. This must be done, however, for all possible combinations of those values a, which are not yet determined, i.e., 2" such evaluations must be made if after this step of the process n values a, are still undetermined. For this purpose an auxiliary quantity V, is introduced which can assume two different values depending on the value a, to be selected during this step: the value a, causing the larger value V is selected as the optimum value. This means that for each decision only a maximum selection from two values has to be effected.

The subscripts of the auxiliary quantity V, indicate that the binary values of the optimum sequence which have to be determined next are the values a, and a,,, with the assumption that m s O and n 2 0. Consequently, if V, has been calculated, the outer values a ,,,...a,,, and a,, ,,...a of the optimum binary sequence are determined whereas the binary values a,,,a and a ...a,, in the middle of the sequence have yet to be determined.

Consider now an example for the purpose of clarification. When a selection is made for a the values of d and a, are assumed to be known. Also, the value of V is known from the decision step for a The value ofV is now modified in dependence ofa a, and a and is then forwarded as V to the decision step for a The quantities V satisfy the following recursion formulae:

.Il-m

By recursive and alternating'application of equations 13a and l3b and under the assumption that V 0 and s, sthe following expression can be obtained:

1 M Vo,o= 2 2'ltu s) 2M g I k? With is term, equation ll can be converted into:

designated V and is no more dependent on a.,;; it is determined for all po ssible sequences [a ..a Using the values of V already calculated,

a,, is chosen during the next step for all possible se- This procedure is schematically represented in the following table:

Number of /M, M=0 evaluations V-2.2(8-2,ai,8n,81,a2) 32 V4.29: 1 amrxol 16 V-1.1(am s Vo.1(ao,a1) 4 Veda) 2 Recursion formulae (16a, 15) must be applied (2"'2) times until the required values V are found. The evaluation effort, however, is much less than it would be for the trivial method of inserting all possible (2 sequencesa'into equation 14 with subsequent evaluation.

The necessary number of operations can be further drastically reduced if the overlapping L on each side of the binary signals stretches over less than 2M basic time intervals (bit intervals) :"L 2M. This condition i is satisfied in most practical cases because M should be chosen larger than L in order to obtain an evaluation interval larger than the area of overlapping. An examination of equations (16a, b) reveals that, for n-m l 2 L, the quantities V, can be split up into two terms,

which can be expressed by the following recursion formulae:

One can now start the optimization at the lower and upper ends of the sequence [a ...a separately and calculate the quantities V and V by applying equations 18a, b, beginning with V and V O. The optimization can be continued in separate branches until n-m l L. At this point, V,,,, and V must be combined in order to obtain V according to equation 17. During subsequent steps equations 16a, b are used to obtain V (a The following two tables show the optimization schemes for M 2, L l and M 3, L 2, respectively. These tables make it obvious how much the effort can be reduced by splitting up the evaluation. The two examples correspond to the embodiments of FIGS. 6 and 7 which are explained later on.

M 2, L 1: (corresponding to FIG. 6)

Number of Evaluations Having thus exhaustively explained the theory of the present invention in terms of how the correction term signal is optimally generated, there will follow a description of a hardware implementation of the invention. Recursion formulae 160, b and 18a, b are to be realized in hardware for an equalizer which generates the correction term K according to the method described above. These formulae require as is shown later on in more detail with the aid of an example that two sums be formed from various quantities and that the larger of these sums be selected. This task can be executed by a decision element schematically shown in FIG. A which performs the following function:

a Max ela 2 e2) Addends of the two sums are represented by groups of input voltages u and a and the result, i.e., the maximum of the two sums, is represented by output voltage 14,.

Details of circuitry which could be used for the decision element are shown in FIG. 58. Each of the inputs 21a ...2lc of the first group is connected to summing point 31 by a resistor R. Inputs 22a...22c are connected to summing point 32 by resistors R in the same manner. Summing points 31, 32 are each connected to the input of an operational amplifier 41, 42. Outputs of these two operational amplifiers are each connected by a diode 51, 52 to junction 33 which in turn is connected to the common output 23. Summing points 31, 32 are also connected each by a diode 61, 62 to the output of the corresponding amplifier 41, 42 and by a resistor 71, 72 to the common junction 33.

This circuit operates as follows: Each half of the circuit represents per se an inverting half-wave rectifier. Due to the connection of the two outputs only the smaller of the two inverted sums is preserved. Consequently, of the two sums of input voltages the larger one is available at the output of the circuit of FIG. 5B but the polarity is inverted. At the amplifier with the larger sum of voltages at its input (e.g., 41), the parallel diode 61 is closed whereas a compensating current can flow through-the other diode 51. Consequently, the sums of input currents i is flowing through the resistor 71 between summing point 31 and common output 33/23; the voltage at the latter is, therefore, equal to the inverted sum of the input voltages of the respective group. At the other amplifier (i.e., 42) the diode 52 between output and summing point is closed whereas a compensating current can flow through the parallel diode 62. A partial input to this branch is the sum of input currents i of the respective group; therefore, the voltage at the common output 23/33 is independent of the input voltages of this second group.

The circuit of FIG. 5B furnishes a voltage u, at its output and must be completed by an inverter at the output for obtaining the decision element of FIG. 5A. In the embodiments shown in FIGS. 6 and 7 the decision elements correspond to FIG. 5A and, therefore, perform the function of equation 19. In principle, decision elements without inverters, as shown in FIG. SB, could also be used. In this case, however, the polarities of the four diodes as well as of the input signals y and s must be reversed in each secondstage.

Analog to the multiple sequential application of the recursion formulae 16a, b and 18a, b, each time with different values for the quantities to obtain a final result, several decision elements of the type just described must be interconnected in a cascaded manner,

The value of V is not only dependent on a but also on a and a Because the values of the latter two are unknown, four evaluations have to be made in this stage, i.e., four decision elements must be provided. For one of these elements the assumption is made that e.g., (1. -l and a +1. With 'l 2(y2+ 1 2)l Inserting first the value +1 and then the value 1 for the binary quantity a leads to the following:

-l, y Max [I -2. y2+ 1 2}, l -z. y-2 1 2 ll Decision element 219 in FIG. 7 corresponds exactly to this equation. The input voltages represent two values V and some selected y and s values; at the output a new value V is available for further processing in tw subsequent decision elements.

DESCRIPTION OF THE EMBODIMENT OF FIG. 6 WHEREIN M 2, L 1

FIG. 6 represents an equalizer for an evaluation interval of four bit periods (4T; M 2) and an overlapping of two bit periods (L 1). Its input is the matched filter 111 connected to tapped delay line 113. Lines 115 and 117 carry signals x(t) and y(t), as shown in FIGS. 2A and 23. An amplifier l19'is connected to center tap y and furnishes the output voltage 2y Inverters 121, 123, 125 and 127 are connected to the 7 other taps so that the tap output voltages y, are also available as inverted signals -y,. A storage 129 is provided for the values of s, and S-p Inverters 131 and 133 connected to the storage outputs also furnish these voltages with inverted polarity. The storage is loaded from inputs A and B by input circuit 135 when a control signal ST is applied on control line 137. Inputs A and B can be connected to output taps y and y in this case, control pulse ST is applied when the maximum of a single test pulse has reached tap y Storage 129 can also be loaded, however, from another storage or from a computing unit. I

The evaluation network is shown in the lower part of FIG. 6. Connecting lines are provided between outputs of the upper part and inputs of the lower part carrying the same designations; however, these lines are not shown in the drawing for simplicity reasons (the same applies to FIG. 7).

The values of V for a l are generated in decision elements 141 and 143. According to formula 18a only the values of :t s, and i y, are required as input. No input is necessary for the initial value of V (V because it is assumed to be 0. The same applies analogously to decision elements 145 and 147. The next stage includes decision elements 149, 151, 153 and 155; besides two signals for is, and i y (or isand i y, respectively), one signal is applied for a quantity V (or V respectively) available from the decision elements of the preceding stage. The association of signals to the decision elements is made in accordance with equations 18a or l8b, respectively.

Signals V,,, ,(--l) and V (-1) are added to obtain V A-l); signals V (+l) and V ,,(-i: l) are added to obtain Vo,0(+1). For generating K2 ,vu,0( ll) is substracted from V (+1) according to equation 13. F1 nally, K2 and 23 0 are added. For all of the last m e n; tioried adding and substracting operationsone single summing circuit 157 is provided in FIG. 6. Consequently, no separate signal for the correctionterm is found in FIG 6. Signal 2(1) appearing on output 159 is sampled with a frequency corresponding to the bit rate; its sign determines whether the final output, which corresponds to the received signal value y is +1 or I.

The embodiment of FIG. 7 essentially corresponds to one just described, except that now M 3 and L 2. Consequently, the delay line 203 connected to filter 201 has seven output taps for signals y ...y Storage 205 is provided to accept four values for s s,, s and s. at its inputs A, B, C and D. Ally values (except y and all r values are also available with inverted signal via appropriate inverters shown but not numbered.

Decision elements 207...245 are connected to each other, to the outputs of delay line 203 and storage 205, and to the outputs of the inverters in accordance with equations l8a and lSb. Since two s values (is is, or is- :s are required for each input group due to the extended overlapping, each decision element has two inputs more than in FIG. 6, and in each stage twice the number of elements are required.

In contrast to FIG. 6, combination of the left and right halves is not achieved here by adding V, and V to obtain V instead, V is obtained by adding V and V Four decision elements can thus be saved. However, a further stage consisting of two decision elements is required for evaluating the four values of V to obtain two values for for V The subtracting operation V ,o(+1)Vo,0(1) for obtaining K2, and the addition of K2 and 231,, to obtain 2(t) are in this case also combined in summing circuit 251. Finally, signal 2(a) is evaluated as described above. Ktifibitfi? cascaded structure shown in FIG. 6 and FIG. 7, only one group of decision elements could be provided as well, using it several times and each time with different input values so that the evaluations would be effected sequentially and not simultaneously.

Thus a major part of the decision elements could be saved; however, a sequencing control and intermediate storage for the intermediate results would be required in this case.

The disclosed decision networks 1 for non-linear weighting of the delay line tap output signals in an equalizer for bipolar binary. signals are well suited for integrated circuit technology because the individual elements show a relatively simple design and are all identical.

The somewhat higher circuit expenditure in comparison to known equalizers of similar basic design is justified in many cases because of the higher probability that received messages are error-free, e.g., in satellite and space communications.

An important advantage of the present invention is the readiness of the equalizer for immediate operation. The frequently used adaptive equalizers often require several seconds for the adaption process, this time delay is not acceptable in e.g., data transmission between data processing systems which often lasts only a few milliseconds. A further advantage in comparison to linear equalizers is' the fact that the remaining part of the noise signal still existing at the output of the entrance filter is not intensified by the delay line filter unit.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

1. A device for equalizing distortion and errors due to overlapping binary bipolar signals, comprising transversal filter means wherein said transversal filter means include, a delay line having 2M+l tap points, wherein M is an integer, means for obtaining from said 2M+l tap points 2M+l sampling values y, at a predetermined sampling interval of the input signal, said tap points and consequently said sampling values being displaced from each other one bit width, means for generating reference values 5, corresponding to at least part of the sampling values which are generated when a single binary value is transmltted, means for non-linearly combining said sampling values and reference values in order to generate an output signal 2 2y wherein y is the sampling value obtained from the mid-tap point on said delay line and corresponds to the difference of signals which are obtained in the combining means utilizing the sampling values and reference values and their corresponding inverted values wherein only the operations of addition and the selection of maxima are effected in the generation of said value.

2. An equalization device as set forth in claim 1 wherein said combining means includes a plurality of decision elements (14!...155, FIG. 6; 207...249, FIG. 7) each of which generates two sum signals from input signals applied to it two groups of inputs and delive s an output signal (V) corresponding E the larEr of the two sum signals, and that the decision elements are arranged in blocks, each block containing at least one decision element and interconnected in a cascaded manner.

3. An equalization device as set forth in claim 2 wherein said decision elements in each of the two input groups include means for connecting the output signal (V) of a decision element from a preceding block to at least one input of a succeeding decision element, one signal selected from the group y, and -y, to another input, and one signal selected from the group comprising s, and s, to the remaining inputs, the signals y, and s, of one input group being inverted with respect to those of the other input group of the same decision element; and at least one summing circuit (156, FIG. 6; 251, FIG. 7) for combining the output signals (V V V.0) from the last block of decision elements with a signal Zy connected to the outputs of said last block of decision elements to produce an output signal z.

4. An equalization device as set forth in claim 3 including means in one block of decision elements (247, 249; FIG. 7) for applying the output signal (V,,, V of a decision element of the preceding block to each of two inputs of each input group so that in this block in each input group, the sum (V,,,,,,) of two decision element output signals is used.

5. An equalization device as set forth in claim 1 wherein said evaluation means (l41...157, FIG. 6) includes means for computing the correction term in accordance with the equation where 0, represents a binary value +1 or -1 and 4 1 represents a sequence of binary values a ...a a ma where 2' has the meaning that the subscript value i-O is not considered in the summation.

6. An equalization device as set forth in claim 1 wherein said evaluation and combination means includes decision units (14!...155, FIG. 6; 207...249, FIG. 7) including means for generating signals V, for

14 obtaining the optimum value of K from said sampling and reference signals y and s such that each decision unit satisfies the equations Max 0 Max for each decision unit one of the binary quantities a, is equal to +1 for one set of inputs, and is equal to -l for the other set of inputs, whereas all other quantities a are fixed;

the value of L corresponds to the extent of intersymbol interference on one side;

at least one adder-subtracter circuit (159, FIG. 6;

251, FIG. 7) connected to the outputs of the decision units for combining the signals V or V and V respectively, from the decision units of said last generation means.

7. An equalization device as set forth in claim 6 5 wherein means for interconnecting succeeding decision units are provided so that in the transition from an evaluation stage in which the decision units generate intermediate signals of the type 7,,,, or V to an evaluation stage in which the decision units generate intermediate signals of the type V,,, an addition of the intermediate signals corresponding to equal sequences of binary quantities a, is effected by the interconnection means according to the relation V,,, V,,, +7.,

8. An equalization device as set forth in claim 1 wherein said evaluation and combination means includes vdecision units (14l...l55, FIG. 6; 207...249, FIG. 7) including means for generating signals V, for obtaining the optimum value of K from said sampling and reference signals y,- and s,-, such that each decision unit satisfies the equations Max for each decision unit one of the binary quantities a, is equal to +1 for one set of inputs, and is equal to -l for the other set of inputs, whereas all other quantities a are fixed;

bol interference on one side;

at least one adder-subtracter circuit (159, FIG. 6;

251, FIG. 7) connected to the outputs of the decision units for combining the signals V or V and V respectively, from the decision units of said last generation means.

the value of L corresponds to the extent of intersym 

1. A device for equalizing distortion and errors due to overlapping binary bipolar signals, comprising transversal filter means wherein said transversal filter means include, a delay line having 2M+1 tap points, wherein M is an integer, means for obtaining from said 2M+1 tap points 2M+1 sampling values yi at a predetermined sampling interval of the input signal, said tap points and consequently said sampling values being displaced from each other one bit width, means for generating reference values si corresponding to at least part of the sampling values which are generated when a single binary value is transmitted, means for non-linearly combining said sampling values and reference values in order to generate an output signal z 2y0 + Kappa , wherein y0 is the sampling value obtained from the mid-tap point on said delay line and Kappa corresponds to the difference of signals which are obtained in the combining means utilizing the sampling values and reference values and their corresponding inverted values wherein only the operations of addition and the selection of maxima are effected in the generation of said Kappa value.
 2. An equalization device as set forth in claim 1 wherein said combining means includes a plurality of decision elements (141...155, FIG. 6; 207...249, FIG. 7) each of which generates two sum signals from input signals applied to it in two groups of inputs and delivers an output signal corresponding to the larger of the two sum signals, and that the decision elements are arranged in blocks, each block containing at least one decision element and interconnected in a cascaded manner.
 3. An equalization device as set forth in claim 2 wherein said decision elements in each of the two input groups include means for connecting the output signal (V) of a decision element from a preceding block to at least one input of a succeeding decision element, one signal selected from the group yi and -yi to another input, and one signal selected from the group comprising si and -si to the remaining inputs, the signals yi and si of one input group being inverted with respect to those of the other input group of the same decision element; and at least one summing circuit (156, FIG. 6; 251, FIG. 7) for combining the output signals (V0,0; V0, , V ,0) from the last block of decision elements with a signal 2y0 connected to the outputs of said last block of decision elements to produce an output signal z.
 4. An equalization device as set forth in claim 3 including means in one block of decision elements (247, 249; FIG. 7) for applying the output signal (Vm,, V ,n) of a decision element of the preceding block to each of two inputs of each input group so that in this block in each input group, the sum (Vm,n) of two decision element output signals is used.
 5. An equalization device as set forth in claim 1 wherein said evaluation means (141...157, FIG. 6) includes means for computing the correction term kappa in accordance with the equation
 6. An equalization device as set forth in claim 1 wherein said evaluation and combination means includes decision units (141...155, FIG. 6; 207...249, FIG. 7) including means for generating signals V, for obtaining the optimum value of kappa from said sampling and reference signals yi and si, such that each decision unit satisfies the equations
 7. An equalization device as set forth in claim 6 wherein means for interconnecting succeeding decision units are provided so that in the transition from an evaluation stage in which the decision units generate intermediate signals of the type Vm, or V ,n to an evaluation stage in which the decision units generate intermediate signals of the type Vm,n, an addition of the intermediate signals corresponding to equal sequences of binary quantities ai is effected by the interconnection means according to the relation Vm,n Vm, +V ,n.
 8. An equalization device as set forth in claim 1 wherein said evaluation and combination means includes decision units (141...155, FIG. 6; 207...249, FIG. 7) including means for generating signals V, for obtaining the optimum value of kappa from said sampling and reference signals yi and si, such that each decision unit satisfies the equations 